1. Field of the Invention
The present invention relates to methods for fabricating interposers, and more particularly, to a method for fabricating an interposer so as to improve the product yield.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIG. 1 is a schematic cross-sectional view of a 3D chip stack package. Referring to FIG. 1, a silicon interposer 1 is provided. The silicon interposer 1 has a chip mounting side 10a, an external connection side 10b opposite to the chip mounting side 10a and having an RDL (redistribution layer) structure 101 formed thereon, and a plurality of through silicon vias (TSVs) 100 communicating the chip mounting side 10a and the external connection side 10b. A semiconductor chip 9 having a plurality of electrode pads 90 is disposed on the chip mounting side 10a of the silicon interposer 1 and the electrode pads 90 are electrically connected to the chip mounting side 10a of the silicon interposer 1 through a plurality of solder bumps 102. The electrode pads 90 have a small pitch therebetween. Further, an underfill 92 is formed between the semiconductor chip 9 and the chip mounting side 10a of the silicon interposer 1 for encapsulating the solder bumps 102, and an encapsulant 8 is formed on the chip mounting side 10a of the silicon interposer 1 for encapsulating the semiconductor chip 9. A packaging substrate 7 having a plurality of bonding pads 70 is disposed on the external connection side 10b of the silicon interposer 1 and the bonding pads 70 are electrically connected to the RDL structure 101 through a plurality of conductive elements 103 such as bumps. Further, an underfill 72 is formed between the packaging substrate 7 and the RDL structure 101 for encapsulating the conductive elements 103. The bonding pads 70 of the packaging substrate 7 have a large pitch therebetween.
FIGS. 1A to 1F are schematic cross-sectional and perspective views showing a method for fabricating a silicon interposer according to the prior art.
Referring to FIG. 1A, a wafer 10 that has gone through a wiring process but is not singulated is provided. The wafer 10 consists of a plurality of silicon interposers 1 of FIG. 1F (detailed structure of the wafer 10 can refer to FIG. 1F). The chip mounting side 10a of the wafer 10 is covered with a protection layer 110 of a support member 11 and the solder bumps 102 are embedded in the protection layer 110.
Referring to FIG. 1B, the wafer 10 is bonded to a first adhesive film 120 of a first carrier 12 via the external connection side 10b thereof, and the conductive elements 103 are embedded in the first adhesive film 120.
Referring to FIG. 1C, the support member 11 and the protection layer 110 of the support member 11 are removed to expose the chip mounting side 10a of the wafer 10.
Referring to FIG. 1C-1, a pre-cutting process is performed on the first adhesive film 120 so as to form a plurality of V-shaped pre-cutting paths 121 on the first adhesive film 120.
Referring to FIG. 1C-2, the chip mounting side 10a of the wafer 10 is fixed by a mechanical arm 5 through such as vacuum adsorption.
Referring to FIG. 1C-3, the overall structure is turned upside down and then the mechanical arm 5 is removed. Thereafter, the overall structure is positioned through the pre-cutting paths 121 and fixed on a positioning plate 4 via the chip mounting side 10a. Subsequently, the first adhesive film 120 is cured.
Referring to FIG. 1C-4, the first carrier 12 is fixed by another mechanical arm 5′ through such as vacuum adsorption.
Referring to FIG. 1C-5, the positioning plate 4 is removed and a second carrier 13 is bonded to the chip mounting side 10a of the wafer 10 through a second adhesive film 130. The solder bumps 102 are embedded in the second adhesive film 130.
Referring to FIG. 1D, the mechanical arm 5′ and the first carrier 12 are removed, and the first adhesive film 120 is removed through the precutting paths 121.
Referring to FIG. 1E, a singulation process is performed. In particular, by using a laser machine 6, a stealth dicing process is performed on the external connection side 10b of the wafer 10, thereby forming a plurality of silicon interposers 1.
Referring to FIG. 1F, the silicon interposers 1 are taken out by a mechanical arm (not shown).
In the above-described method, if the wafer 10 is singulated by laser from the chip mounting side 10a, specific wiring on the chip mounting side 10a of the wafer 10 will prevent a laser beam from passing therethrough. Hence, after the support member 11 and the protection layer 110 are removed, a process of remounting the second carrier 13 to the chip mounting side 10a of the wafer 10 through the second adhesive film 130 is required so as to allow the external connection side 10b of the wafer 10 to face up for singulation.
However, such a remounting process is quite complicated and needs a lot of steps (as shown in FIGS. 1C-1 to 1C-5). Consequently, the wafer 10, which has a thickness of only 100 um, easily cracks or falls off when it is, for example, turned upside down and positioned in FIG. 1C-3, and a delamination easily occurs to the second adhesive film 130 when the first adhesive film 120 is removed in the process of FIG. 1D. As such, the product yield is reduced and the fabrication cost is increased.
Therefore, there is a need to provide a method for fabricating an interposer so as to overcome the above-described drawbacks.